Image sensors are known in the art. They typically comprise a rectangular pixel array for converting light intensity into voltages, which are digitized for providing digital image data.
In several applications the image sensor needs to read certain pre-defined windows or sub-pictures, also called “Region-of-Interest” (ROI). Examples of such applications are machine vision applications and digital still applications. Especially in the case of high resolution devices (e.g. 4000×2000 pixels) in combination with a low resolution ROI (e.g. 100×100 pixels), the readout of the sub-picture may not be optimal. High-resolution devices very often have high-speed circuitry to maintain an acceptable frame rate (e.g. 10 frames/sec). This may realized by means of a column-level ADC configuration. FIG. 1 shows a block-diagram of an example of a prior art two-dimensional image sensor with 16 columns and 9 rows. The image sensor has an on-chip column-level ADC configuration. Every (analog) column is connected to a sample-and-hold circuit (buffer S&H) and to an analog-to-digital converter (ADC). The normal read-out of the sensor is driven by the row select (RS) lines. Although the column-level ADC architecture is very effective for full-resolution high-speed applications, it has some disadvantages in terms of speed and power consumption when only a Region-Of-Interest (or sub-picture) needs to be read out.
US2009/0040349 discloses methods, apparatuses and systems providing a high dynamic range mode of operation for an image sensor when operating in a skip mode where certain pixels of an array are not read out. Multiple integration periods are employed in the skip mode with selected pixels being read out through circuits associated with pixels that are not read out.